The present invention relates generally to methods and systems for semiconductor-manufacturing process estimating intended to evaluate and manage circuit patterns formed on semiconductor wafers. More particularly, the invention relates to a method and apparatus for estimating a cross-sectional shape of a pattern using a SEM image.
The characteristics of conventional transistor devices depend primarily on the width of gate wiring (gate length), and during semiconductor-manufacturing processes, the width of pattern wiring has been mainly measured and managed using critical-dimension scanning electron microscopy (CD-SEM). However, as the formation of finer-structured semiconductor circuit patterns accelerated the tendency towards shorter channeling of transistors, the cross-sectional shapes of the semiconductor patterns have become more important as one of major influential factors upon the transistor device characteristics, in addition to the above-mentioned wiring width.
Japanese Patent Laid-Open No. Hei 10-125749 describes an inspection apparatus for semiconductor products and a method for manufacturing a semiconductor product, which are intended to determine the acceptability of processed patterns formed on a surface to be processed, by matching parameters, combining a simulated three-dimensional geometric model (ideal image) and the three-dimensional image data acquired from the surface to be processed, displaying the combined image on a display screen, and conducting evaluations based on display results.